"Failure Localization of Logic Circuits Using Voltage Contrast Considering ..."

Masafumi Nikaido et al. (2013)

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DOI: 10.1109/ATS.2013.21

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Masafumi Nikaido, Yukihisa Funatsu, Tetsuya Seiyama, Junpei Nonaka, Kazuki Shigeta:
Failure Localization of Logic Circuits Using Voltage Contrast Considering State of Transistors. Asian Test Symposium 2013: 67-72

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