"Architecture for Reliable Scan-Dump in the Presence of Multiple ..."

Amitava Majumdar et al. (2017)

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DOI: 10.1109/ATS.2017.36

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-18

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Amitava Majumdar, Balakrishna Jayadev, Da Cheng, Albert Lin:
Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs. ATS 2017: 139-144

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