"A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector ..."

Zhao Zhang et al. (2019)

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DOI: 10.1109/A-SSCC47793.2019.9056913

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-29

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Zhao Zhang, Guang Zhu, Can Wang, Li Wang, C. Patrick Yue:
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. A-SSCC 2019: 241-242

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