"A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded ..."

Yen-Kuei Lu et al. (2021)

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DOI: 10.1109/A-SSCC53895.2021.9634705

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-21

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Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin:
A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth. A-SSCC 2021: 1-3

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