"Layout techniques for on-chip interconnect inductance reduction."

Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang (2004)

> Home

Details and statistics

DOI: 10.1109/ASPDAC.2004.127

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/aspdac/TuJC04
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/aspdac/TuJC04
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang:
Layout techniques for on-chip interconnect inductance reduction. ASP-DAC 2004: 269-273

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.