"Robust analytical gate delay modeling for low voltage circuits."

Anand Ramalingam et al. (2006)

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DOI: 10.1109/ASPDAC.2006.1594646

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - https://dblp.org/rec/conf/aspdac/RamalingamKDP06
Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan:
Robust analytical gate delay modeling for low voltage circuits. ASP-DAC 2006: 61-66

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