"Hierarchical fault tracing for VLSI sequential circuits from CAD layout ..."

Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka (1997)

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DOI: 10.1109/ASPDAC.1997.600173

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system. ASP-DAC 1997: 329-332

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