"Design of gate-leakage-based timer using an amplifier-less replica-bias ..."

Atsuki Kobayashi et al. (2019)

> Home

Details and statistics

DOI: 10.1145/3287624.3287756

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/aspdac/KobayashiNHAN19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/aspdac/KobayashiNHAN19
Atsuki Kobayashi, Yuya Nishio, Kenya Hayashi, Shigeki Arata, Kiichi Niitsu:
Design of gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS. ASP-DAC 2019: 9-10

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.