"Fault simulation and test generation for clock delay faults."

Yoshinobu Higami et al. (2011)

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DOI: 10.1109/ASPDAC.2011.5722299

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Fault simulation and test generation for clock delay faults. ASP-DAC 2011: 799-805

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