"An Efficient Two-Level Partitioning Algorithm for VLSI Circuits."

Jong-Sheng Cherng et al. (1999)

> Home

Details and statistics

DOI: 10.1109/ASPDAC.1999.759712

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/aspdac/CherngCTH99
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/aspdac/CherngCTH99
Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho:
An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. ASP-DAC 1999: 69-72

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.