"Timing Optimization of Logic Network Using Gate Duplication."

Chun-hong Chen, Chi-Ying Tsui (1999)

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DOI: 10.1109/ASPDAC.1999.760003

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Chun-hong Chen, Chi-Ying Tsui:
Timing Optimization of Logic Network Using Gate Duplication. ASP-DAC 1999: 233-236

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