"An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW ..."

Liang-Bi Chen et al. (2009)

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DOI: 10.1109/ASPDAC.2009.4796467

access: closed

type: Conference or Workshop Paper

metadata version: 2017-09-16

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  - https://dblp.org/rec/conf/aspdac/ChenGHWSHCHLH09
Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang:
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. ASP-DAC 2009: 131-132

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