"Roles of the gate length and width of the transistors in increasing the ..."

Zhongshan Zheng et al. (2017)

> Home

Details and statistics

DOI: 10.1109/ASICON.2017.8252451

access: closed

type: Conference or Workshop Paper

metadata version: 2018-01-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/asicon/ZhengLCLH17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asicon/ZhengLCLH17
Zhongshan Zheng, Zhentao Li, Gengsheng Chen, Jiajun Luo, Zhengsheng Han:
Roles of the gate length and width of the transistors in increasing the single event upset resistance of SRAM cells. ASICON 2017: 219-221

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.