"The timing control design of 65nm block RAM in FPGA."

Xinrui Zhang et al. (2013)

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DOI: 10.1109/ASICON.2013.6811932

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-17

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Xinrui Zhang, Jian Wang, Dan Chen, Jinmei Lai, Lichun Bao, Xueling Liu:
The timing control design of 65nm block RAM in FPGA. ASICON 2013: 1-4

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