"A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm ..."

Jincheng Yang et al. (2015)

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DOI: 10.1109/ASICON.2015.7517130

access: closed

type: Conference or Workshop Paper

metadata version: 2022-07-18

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Jincheng Yang, Zhao Zhang, Peng Feng, Liyuan Liu, Nanjian Wu:
A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS. ASICON 2015: 1-4

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