"TSVs-aware floorplanning for 3D integrated circuit."

Jieliang Lu et al. (2013)

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DOI: 10.1109/ASICON.2013.6812068

access: closed

type: Conference or Workshop Paper

metadata version: 2020-06-26

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Jieliang Lu, Qin Wang, Jing Xie, Zhigang Mao:
TSVs-aware floorplanning for 3D integrated circuit. ASICON 2013: 1-4

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