"Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based ..."

Honghong Long et al. (2023)

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DOI: 10.1109/ASICON58565.2023.10396538

access: closed

type: Conference or Workshop Paper

metadata version: 2025-03-07

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Honghong Long, Yu Bai, Yanze Li, Jian Wang, Jinmei Lai:
Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm. ASICON 2023: 1-4

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