"A PVT-insensitive all digital CMOS time-to-digital converter based on ..."

Siliang Hua et al. (2015)

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DOI: 10.1109/ASICON.2015.7517127

access: closed

type: Conference or Workshop Paper

metadata version: 2018-07-17

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Siliang Hua, Donghui Wang, Leiou Wang, Yan Liu, Jiarui Li:
A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme. ASICON 2015: 1-4

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