"A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array."

Seong Jin Cho et al. (2011)

> Home

Details and statistics

DOI: 10.1109/ASICON.2011.6157224

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/asicon/ChoHYB11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asicon/ChoHYB11
Seong Jin Cho, Yohan Hong, Taegeun Yoo, Kwang-Hyun Baek:
A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array. ASICON 2011: 472-475

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.