"Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of ..."

H. T. Kung et al. (2019)

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DOI: 10.1109/ASAP.2019.00-31

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-18

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H. T. Kung, Bradley McDanel, Sai Qian Zhang, Xin Dong, Chih-Chiang Chen:
Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays. ASAP 2019: 42-50

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