"An FPGA-based Parallel Hardware Architecture for Real-Time Face Detection ..."

Seunghun Jin et al. (2009)

> Home

Details and statistics

DOI: 10.1109/ASAP.2009.36

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/asap/JinKNJKJ09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asap/JinKNJKJ09
Seunghun Jin, Dongkyun Kim, Thuy Tuong Nguyen, Bongjin Jun, Daijin Kim, Jae Wook Jeon:
An FPGA-based Parallel Hardware Architecture for Real-Time Face Detection Using a Face Certainty Map. ASAP 2009: 61-66

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.