"Timing Driven Placement for Fault Tolerant Circuits Implemented on ..."

Luca Sterpone (2009)

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DOI: 10.1007/978-3-642-00641-8_11

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-14

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Luca Sterpone:
Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs. ARC 2009: 85-96

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