"Panning sorter: A minimal-size architecture for hardware implementation of ..."

Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni (2010)

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DOI: 10.1109/APCCAS.2010.5775035

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni:
Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors. APCCAS 2010: 923-926

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