"Implementation of DDR3 SDRAM multi-channel read and write circuit based on ..."

Zhishuo Wang, Dongming Xu, Yuhao Li (2023)

> Home

Details and statistics

DOI: 10.1145/3641584.3641719

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/aipr2/WangXL23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/aipr2/WangXL23
Zhishuo Wang, Dongming Xu, Yuhao Li:
Implementation of DDR3 SDRAM multi-channel read and write circuit based on FPGA. AIPR 2023: 903-908

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.