"Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing ..."

Michele Mastella et al. (2020)

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DOI: 10.1109/AICAS48895.2020.9073965

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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Michele Mastella, Fabio Toso, Giuseppe Sciortino, Enrico Prati, Giorgio Ferrari:
Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing Dependent Plasticity. AICAS 2020: 213-217

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