"Deploying Artificial Intelligence in Design Verification to Accelerate ..."

Surajit Bhattacherjee, Daksh Shah, Dipankar Pal (2024)

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DOI: 10.1109/AICAS59952.2024.10595855

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-31

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Surajit Bhattacherjee, Daksh Shah, Dipankar Pal:
Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape. AICAS 2024: 477-481

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