"Partial-product generation and addition for multiplication in FPGAs with ..."

E. George Walters III (2014)

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DOI: 10.1109/ACSSC.2014.7094659

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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E. George Walters III:
Partial-product generation and addition for multiplication in FPGAs with 6-input LUTs. ACSSC 2014: 1247-1251

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