default search action
"Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA."
Chi-Chia Sun et al. (2010)
- Chi-Chia Sun, Jürgen Götze, Hong-Yuan Jheng, Shanq-Jang Ruan:
Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA. CIT 2010: 2306-2310
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.