"A built-in test circuit for open defects at interconnects between dies in ..."

Widianto et al. (2011)

> Home

Details and statistics

DOI: 10.1109/3DIC.2012.6263041

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/3dic/WidiantoYOTH11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/3dic/WidiantoYOTH11
Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume:
A built-in test circuit for open defects at interconnects between dies in 3D ICs. 3DIC 2011: 1-5

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.