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David May 0003

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affiliation: European Patent Office, Munich, Germany
affiliation (former): TUM, Munich, Germany

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2010 – 2019

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2016
[c6]
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  - conf/dtis/MayS16
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David May, Walter Stechele:
Voltage over-scaling in sequential circuits for approximate computing. DTIS 2016: 1-6
2015
[c5]
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David May, Walter Stechele:
Design of fine-grained sequential approximate circuits using probability-aware fault emulation. ISLPED 2015: 73-78
2014
[c4]
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  - conf/iolts/MayS14
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David May, Walter Stechele:
Improving the significance of probabilistic circuit fault emulations. IOLTS 2014: 128-133
2013
[c3]
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David May, Walter Stechele:
A resource-efficient probabilistic fault simulator. FPL 2013: 1-4
2012
[c2]
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  - conf/aspdac/BeckerFHKM12
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Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf König, David May:
Hardware prototyping of novel invasive multicore architectures. ASP-DAC 2012: 201-206
[c1]
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David May, Walter Stechele:
An FPGA-based probability-aware fault simulator. ICSAMOS 2012: 302-309

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