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ORCIDShuichi Ichikawa
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2020 – today
- 2023
[j20]Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, Hitomi Kishibe:
Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator. IEICE Trans. Inf. Syst. 106(12): 1940-1950 (2023)- [c23]Shuichi Ichikawa:
Pseudo-Random Number Generation by Staggered Sampling of LFSR. candar 2023: 134-140 - 2022
- [c22]Ryusei Oya, Naoki Fujieda
, Shuichi Ichikawa:
An HLS implementation of on-the-fly randomness test for TRNGs. CANDAR 2022: 151-157 - 2021
- [j19]Shunsuke Matsuoka, Shuichi Ichikawa, Naoki Fujieda:
A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC). Int. J. Circuit Theory Appl. 49(10): 3354-3367 (2021) - 2020
- [j18]Naoki Fujieda, Masaaki Takeda, Shuichi Ichikawa:
An Analysis of DCM-Based True Random Number Generator. IEEE Trans. Circuits Syst. II Express Briefs 67-II(6): 1109-1113 (2020) - [c21]Shotaro Yamada, Shuichi Ichikawa:
Netlist-based Measures for Hardware Obfuscation: A Preliminary Study. CANDAR (Workshops) 2020: 116-119
2010 – 2019
- 2019
- [c20]Naoki Fujieda, Hitomi Kishibe, Shuichi Ichikawa:
A light-weight implementation of latch-based true random number generator. IWCMC 2019: 901-906 - 2018
- [j17]Naoki Fujieda, Shuichi Ichikawa:
A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs. IEICE Electron. Express 15(10): 20180386 (2018) - [j16]Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, Shuichi Ichikawa:
Evaluation of Register Number Abstraction for Enhanced Instruction Register Files. IEICE Trans. Inf. Syst. 101-D(6): 1521-1531 (2018) - [c19]Hiroki Fujita, Naoki Fujieda, Shuichi Ichikawa:
An Analysis on Randomness of Path ORAM for Light-Weight Implementation. CANDAR Workshops 2018: 163-165 - [c18]Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa:
A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity. TENCON 2018: 1489-1492 - 2017
- [j15]Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, Shuichi Ichikawa:
A Virtual Cache for Overlapped Memory Accesses of Path ORAM. Int. J. Netw. Comput. 7(2): 106-123 (2017) - [c17]Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, Shuichi Ichikawa:
An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis. CANDAR 2017: 323-325 - [c16]Seiya Ogido, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa:
A Study of a Fault-Tolerant System Using Dynamic Partial Reconfiguration. CANDAR 2017: 600-602 - [c15]Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, Tasuku Tanaka:
Evaluation of the hardwired sequence control system generated by high-level synthesis. ISIE 2017: 1261-1267 - 2016
- [j14]Naoki Fujieda, Tasuku Tanaka, Shuichi Ichikawa:
Design and implementation of instruction indirection for embedded software obfuscation. Microprocess. Microsystems 45: 115-128 (2016) - [c14]Naoki Fujieda, Ryo Yamauchi, Shuichi Ichikawa:
Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM. CANDAR 2016: 347-353 - 2015
- [c13]Naoki Fujieda, Kiyohiro Sato, Shuichi Ichikawa:
A Complement to Enhanced Instruction Register File against Embedded Software Falsification. PPREW@ACSAC 2015: 3:1-3:7 - 2013
- [c12]Naoki Fujieda, Shuichi Ichikawa:
An XOR-Based Approach to Merging Entries for Instruction Register Files. CANDAR 2013: 332-337 - 2012
- [j13]Hisashi Hata, Shuichi Ichikawa:
FPGA Implementation of Metastability-Based True Random Number Generator. IEICE Trans. Inf. Syst. 95-D(2): 426-436 (2012) - [c11]Shunsuke Matsuoka, Shuichi Ichikawa:
Reduction of Power Consumption in Key-specific AES Circuits. ICNC 2012: 323-325 - [c10]Satoru Tamura, Chikatoshi Yamada, Shuichi Ichikawa:
Implementation and Evaluation of Modular Multiplication Based on Coarsely Integrated Operand Scanning. ICNC 2012: 334-335 - 2011
- [j12]Shuichi Ichikawa:
Foreword. IEICE Trans. Inf. Syst. 94-D(12): 2297 (2011)
2000 – 2009
- 2009
- [j11]Shuichi Ichikawa, Sho Takahashi, Yuu Kawai:
Optimizing process allocation of parallel programs for heterogeneous clusters. Concurr. Comput. Pract. Exp. 21(4): 475-507 (2009) - [c9]Shuichi Ichikawa, Shoichiro Takagi:
Estimating the Optimal Configuration of a Multi-Core Cluster: A Preliminary Study. CISIS 2009: 1245-1251 - 2008
- [j10]Shuichi Ichikawa, Takashi Sawada, Hisashi Hata:
Diversification of Processors Based on Redundancy in Instruction Set. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(1): 211-220 (2008) - 2006
- [j9]Kazuhiro Hattanda, Shuichi Ichikawa:
Redundancy in Instruction Sequences of Computer Programs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(1): 219-221 (2006) - [j8]Ryoichiro Atono, Shuichi Ichikawa:
Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm. IEICE Trans. Inf. Syst. 89-D(7): 2301-2305 (2006) - 2005
- [j7]Shiro Konuma, Shuichi Ichikawa:
Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937. IEICE Trans. Inf. Syst. 88-D(12): 2876-2879 (2005) - [j6]Yoshinori Kishimoto, Shuichi Ichikawa:
Optimizing the configuration of a heterogeneous cluster with multiprocessing and execution-time estimation. Parallel Comput. 31(7): 691-710 (2005) - 2004
- [j5]Kazuhiro Hattanda, Shuichi Ichikawa:
The Evaluation of Davidson's Digital Signature Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 87-A(1): 224-225 (2004) - [j4]Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto:
The Design and Evaluation of Data-Dependent Hardware for Subgraph Isomorphism Problem. IEICE Trans. Inf. Syst. 87-D(8): 2038-2047 (2004) - [c8]Yoshinori Kishimoto, Shuichi Ichikawa:
An Execution-Time Estimation Model for Heterogeneous Clusters. IPDPS 2004 - 2003
- [c7]Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto:
Data Dependent Circuit Design: A Case Study. FPL 2003: 1024-1027 - 2002
- [c6]Shuichi Ichikawa, Shoji Yamamoto:
Data Dependent Circuit for Subgraph Isomorphism Problem. FPL 2002: 1068-1071 - [c5]Shuichi Ichikawa, H. Chiyama, K. Akabane:
Redundancy in 3D Polygon Models and Its Application to Digital Signature. WSCG 2002: 225-232 - 2000
- [c4]Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi:
Hardware Accelerator for Subgraph Isomorphism Problems. FCCM 2000: 283-284 - [c3]Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi:
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem. FPL 2000: 729-738
1990 – 1999
- 1992
- [j3]Shuichi Ichikawa, Mitsuhisa Sato, Eiichi Goto:
Evaluation of range-checking addressing modes and the architecture of FLATS2. Syst. Comput. Jpn. 23(10): 1-13 (1992) - 1991
- [j2]Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa:
Pseudorandom Rounding for Truncated Multipliers. IEEE Trans. Computers 40(9): 1065-1067 (1991) - 1990
- [c2]Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto:
Multiple instruction streams in a highly pipelined processor. SPDP 1990: 182-189
1980 – 1989
- 1989
- [j1]Kentaro Shimizu, Eiichi Goto, Shuichi Ichikawa:
CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines. IEEE Trans. Computers 38(6): 825-832 (1989) - [c1]Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto:
Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking. ISCA 1989: 290-297
Coauthor Index
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