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ORCIDNastaran Baradaran
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2000 – 2009
- 2008
[j2]Nastaran Baradaran, Pedro C. Diniz
:
A compiler approach to managing storage and memory bandwidth in configurable architectures. ACM Trans. Design Autom. Electr. Syst. 13(4): 61:1-61:26 (2008)- 2007
- [j1]Nastaran Baradaran, Pedro C. Diniz:
Exploiting parallelism in configurable architectures through custom array mapping. IET Comput. Digit. Tech. 1(4): 303-311 (2007) - [i1]Nastaran Baradaran, Pedro C. Diniz:
A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures. CoRR abs/0710.4702 (2007) - 2006
- [c7]Nastaran Baradaran, Pedro C. Diniz:
Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures. FPL 2006: 1-6 - 2005
- [c6]Nastaran Baradaran, Pedro C. Diniz:
A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures. DATE 2005: 6-11 - [c5]Nastaran Baradaran, Pedro C. Diniz:
Compiler-Directed Design Space Exploration for Caching and Prefetching Data in High-Level Synthesis. FPT 2005: 233-240 - 2004
- [c4]Nastaran Baradaran, Joonseok Park, Pedro C. Diniz:
Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract. FPL 2004: 1113-1115 - [c3]Nastaran Baradaran, Joonseok Park, Pedro C. Diniz:
Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks. FPT 2004: 145-152 - [c2]Nastaran Baradaran, Pedro C. Diniz, Joonseok Park:
Extending the Applicability of Scalar Replacement to Multiple Induction Variables. LCPC 2004: 455-469 - 2003
- [c1]Nastaran Baradaran, Jacqueline Chame, Chun Chen, Pedro C. Diniz, Mary W. Hall, Yoon-Ju Lee, Bing Liu, Robert F. Lucas:
ECO: An Empirical-Based Compilation and Optimization System. IPDPS 2003: 206
Coauthor Index
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