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Journal Articles
- 2024
[j5]Tomás Rabas
, Jirí Bucek, Róbert Lórencz:
Single-Trace Side-Channel Attacks on NTRU Implementation. SN Comput. Sci. 5(2): 239 (2024)- 2022
- [j4]Filip Kodýtek, Róbert Lórencz, Jirí Bucek:
Three counter value based ROPUFs on FPGA and their properties. Microprocess. Microsystems 88: 104375 (2022) - 2017
- [j3]Simona Buchovecká, Róbert Lórencz, Filip Kodýtek, Jirí Bucek:
True random number generator based on ring oscillator PUF circuit. Microprocess. Microsystems 53: 33-41 (2017) - [j2]Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
Design of a Residue Number System Based Linear System Solver in Hardware. J. Signal Process. Syst. 87(3): 343-356 (2017) - 2016
- [j1]Filip Kodýtek, Róbert Lórencz, Jirí Bucek:
Improved ring oscillator PUF on FPGA and its properties. Microprocess. Microsystems 47: 55-63 (2016)
Conference and Workshop Papers
- 2023
- [c16]Tomás Rabas, Jirí Bucek, Róbert Lórencz:
Single-Trace Attack on NTRU Decryption with Machine Learning and Template Profiling. DSD 2023: 124-129 - [c15]Tomás Rabas, Jirí Bucek, Róbert Lórencz:
SPA Attack on NTRU Protected Implementation with Sparse Representation of Private Key. ICISSP 2023: 135-143 - 2022
- [c14]Tomás Rabas, Róbert Lórencz, Jirí Bucek:
Verification of PUF-based IoT Protocols with AVISPA and Scyther. SECRYPT 2022: 627-635 - 2020
- [c13]Filip Kodýtek, Róbert Lórencz, Jirí Bucek:
Comparison of three counter value based ROPUFs on FPGA. DSD 2020: 205-212 - [c12]Simona Buchovecká, Róbert Lórencz, Jirí Bucek, Filip Kodýtek:
Lightweight Authentication and Secure Communication Suitable for IoT Devices. ICISSP 2020: 75-83 - [c11]Simona Buchovecká, Róbert Lórencz, Jirí Bucek, Filip Kodýtek:
Symmetric and Asymmetric Schemes for Lightweight Secure Communication. ICISSP (Revised Selected Papers) 2020: 97-114 - 2019
- [c10]Martin Jurecek, Jirí Bucek, Róbert Lórencz:
Side-Channel Attack on the A5/1 Stream Cipher. DSD 2019: 633-638 - 2016
- [c9]Simona Buchovecká, Róbert Lórencz, Filip Kodýtek, Jirí Bucek:
True Random Number Generator Based on ROPUF Circuit. DSD 2016: 519-523 - [c8]Martin Rozkovec, Jirí Bucek:
Polynomial Based NUC Implemented on FPGA. DSD 2016: 670-673 - [c7]Filip Kodýtek, Róbert Lórencz, Jirí Bucek, Simona Buchovecká:
Temperature Dependence of ROPUF on FPGA. DSD 2016: 698-702 - 2014
- [c6]Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
An ASIC linear congruence solver synthesized with three cell libraries. ICECS 2014: 706-709 - [c5]Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
System on chip design of a linear system solver. ISSoC 2014: 1-6 - 2013
- [c4]Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver. DSD 2013: 284-287 - [c3]Filip Stepánek, Jirí Bucek, Martin Novotný:
Differential Power Analysis under Constrained Budget: Low Cost Education of Hackers. DSD 2013: 645-648 - 2012
- [c2]Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
Dedicated hardware implementation of a linear congruence solver in FPGA. ICECS 2012: 689-692 - 2006
- [c1]Jirí Bucek, Róbert Lórencz:
Comparing Subtraction-Free and Traditional AMI. DDECS 2006: 97-99
Editorship
- 2006
- [e1]Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek:
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006. IEEE Computer Society 2006, ISBN 1-4244-0185-2 [contents]
Coauthor Index
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last updated on 2024-10-07 22:11 CEST by the dblp team
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