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2020 – today
- 2023
[c18]Chung-Bin Wu, Yi-Yen Lai, Yen-Ren Hou:
System Integration and Optimization of AI Hardware Acceleration Architecture for Object Detection. ICCE-Taiwan 2023: 93-94- 2022
- [c17]Chung-Bin Wu, Yu-Kuan Hsiao, Wei-Hsuan Chang:
Extensible and Modularized Processing Unit Design and Implementation for AI Accelerator. AICAS 2022: 238-241 - [c16]Ko-Yi Jiang, Hsing-Yao Wang, Chung-Bin Wu, Yin-Tsung Hwang, Chih-Peng Fan:
Quantized Lite Convolutional Neural Network Hardware Accelerator Design with FPGA for Face Direction Recognition. ICCE-TW 2022: 61-62 - [c15]Chung-Bin Wu, Rui-Feng Wu, Tzu-Wei Chan:
Hetero Layer Fusion Based Architecture Design and Implementation for of Deep Learning Accelerator. ICCE-TW 2022: 63-64 - [c14]Chung-Bin Wu, Yu-Hu Wu, Yi-Yen Lai:
AI Crowd Control Detection System Implemented on FPGA Hardware Development Platform. ICCE 2022: 1-4 - [c13]Wei-Che Sun, Chih-Peng Fan, Chung-Bin Wu:
Design and FPGA Implementation of Lite Convolutional Neural Network Based Hardware Accelerator for Ocular Biometrics Recognition Technology. MCSoC 2022: 278-283 - 2021
- [c12]Yin-Tsung Hwang, Kuan-Hong Chen, Chih-Peng Fan
, Yong-Kang Lai, Chung-Bin Wu, Hsiao-Ping Tsai, Wei-Liang Lin, Kuang-Hao Lin:
iAMEC, an Intelligent Autonomous Mover for Navigation in Indoor People Rich Environments. AICAS 2021: 1-4 - [c11]Chung-Bin Wu, Chung-Hsuan Chen, Chen-Peng Kuan:
Reconfigurable Deep Learning Accelerator Hardware Architecture Design for Sparse CNN. ICCE-TW 2021: 1-2 - 2020
- [c10]Chung-Bin Wu, Ching-Shun Wang, Yu-Kuan Hsiao:
Reconfigurable Hardware Architecture Design and Implementation for AI Deep Learning Accelerator. GCCE 2020: 154-155 - [c9]Chung-Bin Wu, Yu-Kuan Hsiao:
Cordic Based Hardware Implementation for Object Region Layer of Yolo V2. ICCE-TW 2020: 1-2 - [c8]Chung-Bin Wu, Yin-Tsung Hwang, Yu-Cheng Hsueh, Yu-Kuan Hsiao:
High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator. ISOCC 2020: 193-194
2010 – 2019
- 2019
- [j6]Chung-Bin Wu, Li-Hung Wang, Kuan-Chieh Wang:
Ultra-Low Complexity Block-Based Lane Detection and Departure Warning System. IEEE Trans. Circuits Syst. Video Technol. 29(2): 582-593 (2019) - [c7]Chung-Bin Wu, Yu-Cheng Hsueh, Ching-Shun Wang, Yen-Chi Lai:
High Throughput Hardware Implementation for Deep Learning AI Accelerator. ICCE-TW 2019: 1-2 - [c6]Chung-Bin Wu, Guan-Jing Chen, Chien-Cheng Yu:
Low Complexity License Plate Recognition System. ISOCC 2019: 156-157 - 2017
- [j5]Chung-Bin Wu, Li-Hung Wang, Yu-Lin Chou:
Hardware-and-memory-sharing architecture of deblocking filter for VP8 and H.264/AVC. IEEE Trans. Consumer Electron. 63(3): 216-224 (2017) - 2016
- [j4]Chia-Wei Chang, Hao-Fan Hsu, Chih-Peng Fan, Chung-Bin Wu, Robert Chen-Hao Chang:
A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC. J. Signal Process. Syst. 82(1): 69-89 (2016) - 2015
- [c5]Li-Hung Wang, Kai-Lung Tsai, Chung-Bin Wu:
Object-based stereo matching using adjustable-cross for depth estimation. ICCE-TW 2015: 194-195 - 2014
- [c4]Li-Hung Wang, Chao-Kai Cheng, Chung-Bin Wu:
A real-time architecture of multiple features extraction for vehicle verification. APCCAS 2014: 615-618 - 2012
- [c3]Hsin-Yi Wang, Li-Hung Wang, Chung-Bin Wu:
An efficient background extraction and object segmentation algorithm for realtime applications. APCCAS 2012: 659-662 - [c2]Yu-Lin Chou, Chung-Bin Wu:
A hardware sharing architecture of deblocking filter for VP8 and H.264/AVC video coding. ISCAS 2012: 1915-1918
2000 – 2009
- 2005
- [j3]Chung-Bin Wu, Chin-Yuan Yao, Bin-Da Liu, Jar-Ferr Yang:
DCT-Based Adaptive Thresholding Algorithm for Binary Motion Estimation. IEEE Trans. Circuits Syst. Video Technol. 15(5): 694-703 (2005) - 2003
- [j2]Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang:
Adaptive postprocessors with DCT-based block classifications. IEEE Trans. Circuits Syst. Video Technol. 13(5): 365-375 (2003) - [j1]Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang:
A fuzzy-based impulse noise detection and cancellation for real-time processing in video receivers. IEEE Trans. Instrum. Meas. 52(3): 780-784 (2003) - 2001
- [c1]Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang:
Adaptive postprocessors with DCT-based block classifications. ISCAS (5) 2001: 271-274
Coauthor Index
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