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2010 – 2019
- 2011
[j10]Enric Musoll:
Variable-size mosaics: A process-variation aware technique to increase the performance of tile-based, massive multi-core processors. Comput. Electr. Eng. 37(6): 1193-1211 (2011)- 2010
- [j9]Enric Musoll:
Hardware-Based Load Balancing for Massive Multicore Architectures Implementing Power Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 493-497 (2010) - [j8]Enric Musoll:
A cost-effective load-balancing policy for tile-based, massive multi-core packet processors. ACM Trans. Embed. Comput. Syst. 9(3): 24:1-24:25 (2010) - [c10]Enric Musoll:
Load balancing packets on a tile-based massive multi-core processor with S-NUCA. ANCS 2010: 32
2000 – 2009
- 2009
- [j7]Enric Musoll:
A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors. IEEE Comput. Archit. Lett. 8(2): 52-55 (2009) - [j6]Enric Musoll:
Mesh-based many-core performance under process variations: a core yield perspective. SIGARCH Comput. Archit. News 37(4): 27-34 (2009) - [j5]Enric Musoll:
Leakage-saving opportunities in mesh-based massive multi-core architectures. SIGARCH Comput. Archit. News 37(5): 1-7 (2009) - [c9]Enric Musoll:
Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures. ISQED 2009: 201-207 - 2008
- [j4]Enric Musoll:
Power Gating Clustered Many-Core Architectures. J. Low Power Electron. 4(3): 290-300 (2008) - [c8]Enric Musoll:
A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors. ISQED 2008: 549-552 - [c7]Enric Musoll:
Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating. SASP 2008: 89-94 - 2003
- [j3]Enric Musoll:
Speculating to reduce unnecessary power consumption. ACM Trans. Embed. Comput. Syst. 2(4): 509-536 (2003)
1990 – 1999
- 1999
- [c6]Enric Musoll:
Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors. MICRO 1999: 238-247 - 1998
- [j2]Enric Musoll, Jordi Cortadella:
Register-Transfer Level Transformations for Low-Power Data-Paths. Integr. Comput. Aided Eng. 5(4): 315-332 (1998) - [j1]Enric Musoll, Tomás Lang, Jordi Cortadella
:
Working-zone encoding for reducing the energy in microprocessor address buses. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 568-572 (1998) - [c5]Tomás Lang, Enric Musoll, Jordi Cortadella:
Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus. ICCD 1998: 414-419 - 1997
- [c4]Enric Musoll, Tomás Lang, Jordi Cortadella:
Exploiting the locality of memory references to reduce the address bus energy. ISLPED 1997: 202-207 - 1996
- [c3]Enric Musoll, Jordi Cortadella:
Optimizing CMOS Circuits for Low Power Using Transistor Reordering. ED&TC 1996: 219-223 - 1995
- [c2]Enric Musoll, Jordi Cortadella:
High-level synthesis techniques for reducing the activity of functional units. ISLPD 1995: 99-104 - [c1]Enric Musoll, Jordi Cortadella:
Scheduling and resource binding for low power. ISSS 1995: 104-109
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