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David Zaretsky
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Journal Articles
- 2007
- [j2]Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee:
An Overview of a Compiler for Mapping Software Binaries to Hardware. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1177-1190 (2007) - 2004
- [j1]Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, Robert Anderson, Juan Ramon Uribe:
Overview of a compiler for synthesizing MATLAB programs onto FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 312-324 (2004)
Conference and Workshop Papers
- 2011
- [c14]Lei Gao, Gaurav Mittal, David Zaretsky, Prith Banerjee:
Resource optimization and deadlock prevention while generating streaming architectures from ordinary programs. AHS 2011: 9-16 - 2010
- [c13]Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee:
Automatic Generation of Stream Descriptors for Streaming Architectures. ICPP 2010: 307-312 - 2009
- [c12]Gaurav Mittal, David Zaretsky, Prithviraj Banerjee:
Streaming implementation of a sequential decompression algorithm on an FPGA. FPGA 2009: 283 - [c11]Lei Gao, Gaurav Mittal, David Zaretsky, Dan Schonfeld, Prithviraj Banerjee:
An Automated Algorithm to Generate Stream Programs. ISCAS 2009: 1505-1508 - [c10]David Zaretsky, Gaurav Mittal, Prithviraj Banerjee:
Streaming Implementation of the ZLIB Decoder Algorithm on an FPGA. ISCAS 2009: 2329-2332 - [c9]Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee:
A software pipelining algorithm in high-level synthesis for FPGA architectures. ISQED 2009: 297-302 - 2007
- [c8]David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs. ISQED 2007: 595-601 - 2006
- [c7]David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs. VLSI Design 2006: 465-468 - 2005
- [c6]Gaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee:
Automatic extraction of function bodies from software binaries. ASP-DAC 2005: 928-931 - [c5]David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code. LCPC 2005: 76-90 - 2004
- [c4]Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee:
Automatic translation of software binaries onto FPGAs. DAC 2004: 389-394 - [c3]David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee:
Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. FCCM 2004: 37-46 - [c2]David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee:
Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. ACM Great Lakes Symposium on VLSI 2004: 397-400 - 2000
- [c1]Prithviraj Banerjee, U. Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky:
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. FCCM 2000: 39-48
Coauthor Index
aka: Prith Banerjee
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