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2020 – today
- 2022
[j2]Martin Straka
, Martin Hricko:
Software system design for solution of effective material layout for the needs of production and logistics. Wirel. Networks 28(2): 873-882 (2022)
2010 – 2019
- 2013
- [b1]Martin Straka:
Metodologie pro návrh číslicových obvodů se zvýšenou spolehlivostí ; Methodology of highly reliable systems design. Brno University of Technology, Czech Republic, 2013 - [j1]Martin Straka, Jan Kastil, Zdenek Kotásek, Lukas Miculka:
Fault tolerant system design and SEU injection based testing. Microprocess. Microsystems 37(2): 155-173 (2013) - [c12]Karel Szurman, Jan Kastil, Martin Straka, Zdenek Kotásek:
Fault tolerant CAN bus control system implemented into FPGA. DDECS 2013: 289-292 - [c11]Lukas Miculka, Martin Straka, Zdenek Kotásek:
Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area. DSD 2013: 227-234 - 2012
- [c10]Martin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotásek:
Test platform for fault tolerant systems design properties verification. DDECS 2012: 336-341 - [c9]Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotásek:
Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. DSD 2012: 250-257 - 2011
- [c8]Martin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek:
Advanced fault tolerant bus for multicore system implemented in FPGA. DDECS 2011: 397-398 - [c7]Martin Straka, Jan Kastil, Zdenek Kotásek:
SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems. DSD 2011: 223-230 - 2010
- [c6]Martin Straka, Jan Kastil, Zdenek Kotásek:
Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs. DDECS 2010: 173-176 - [c5]Martin Straka, Jan Kastil, Zdenek Kotásek:
Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. DSD 2010: 365-372
2000 – 2009
- 2009
- [c4]Martin Straka, Zdenek Kotásek:
High Availability Fault Tolerant Architectures Implemented into FPGAs. DSD 2009: 108-115 - 2008
- [c3]Martin Straka, Zdenek Kotásek, Jan Winter:
Digital Systems Architectures Based on On-line Checkers. DSD 2008: 81-87 - 2007
- [c2]Martin Straka, Jiri Tobola, Zdenek Kotásek:
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. DFT 2007: 152-160 - [c1]Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka:
Online Protocol Testing for FPGA Based Fault Tolerant Systems. DSD 2007: 676-679
Coauthor Index
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