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2020 – today
- 2024
[j3]Yi-Shan Lu, Chien-Shu Tsai
, Jen-Yao Lee, Chung-Yang Lee:
Collusive Stability with Relative Performance and Network Externalities. Games 15(3): 21 (2024)- 2021
- [j2]Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali:
An Open-Source EDA Flow for Asynchronous Logic. IEEE Des. Test 38(2): 27-37 (2021) - 2020
- [c4]Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar:
Cyclone: A Static Timing and Power Engine for Asynchronous Circuits. ASYNC 2020: 11-19
2010 – 2019
- 2018
- [c3]Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis:
Unlocking fine-grain parallelism for AIG rewriting. ICCAD 2018: 87 - [p1]Yi-Shan Lu, Keshav Pingali:
Can Parallel Programming Revolutionize EDA Tools? Advanced Logic Synthesis 2018: 21-41 - 2017
- [c2]Chad Voegele, Yi-Shan Lu, Sreepathi Pai, Keshav Pingali:
Parallel triangle counting and k-truss identification using graph-centric methods. HPEC 2017: 1-7 - 2013
- [j1]Chen Kang Lo, Mao Lin Li, Li-Chun Chen, Yi-Shan Lu, Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh:
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus. ACM Trans. Embed. Comput. Syst. 13(1s): 37:1-37:25 (2013) - 2012
- [c1]Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, Ren-Song Tsay:
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation. DAC 2012: 127-132
Coauthor Index
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