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Journal Articles
- 2010
[j12]Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda:
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. IEICE Trans. Electron. 93-C(3): 295-302 (2010)- [j11]Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa:
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. IEEE J. Solid State Circuits 45(6): 1091-1098 (2010) - [j10]Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker:
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits 45(10): 2016-2029 (2010) - 2009
- [j9]Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. IEEE J. Solid State Circuits 44(12): 3580-3589 (2009) - 2008
- [j8]Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda:
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. IEEE J. Solid State Circuits 43(3): 610-618 (2008) - 2007
- [j7]Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda:
18-GHz Clock Distribution Using a Coupled VCO Array. IEICE Trans. Electron. 90-C(4): 811-822 (2007) - [j6]Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda:
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. IEEE J. Solid State Circuits 42(3): 627-636 (2007) - [j5]Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. IEEE J. Solid State Circuits 42(12): 2726-2735 (2007) - 2006
- [j4]Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa:
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. IEICE Trans. Electron. 89-C(3): 300-313 (2006) - 2005
- [j3]Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda:
A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. IEEE J. Solid State Circuits 40(4): 986-993 (2005) - [j2]Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda:
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE J. Solid State Circuits 40(8): 1680-1687 (2005) - 1998
- [j1]Miyoshi Saito, Junji Ogawa, Hirotaka Tamura, Shigetoshi Wakayama, Hisakatsu Araki, Tsz-Shing Cheung, Kohtaroh Gotoh, Tadao Aikawa, Takaaki Suzuki, Masao Taguchi, Takeshi Imamura:
500-Mb/s nonprecharged data bus for high-speed DRAM's. IEEE J. Solid State Circuits 33(11): 1720-1730 (1998)
Conference and Workshop Papers
- 2010
- [c7]Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh:
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. ISSCC 2010: 168-169 - 2009
- [c6]Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda:
Split capacitor DAC mismatch calibration in successive approximation ADC. CICC 2009: 279-282 - [c5]Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. ISSCC 2009: 360-361 - 2007
- [c4]Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. ISSCC 2007: 224-598 - 2006
- [c3]Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda:
A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. ISSCC 2006: 2102-2111 - 2005
- [c2]Yoshiyasu Doi, Syunitirou Masaki, Takaya Chiba, Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura:
A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process. CICC 2005: 131-134 - 2000
- [c1]Junji Ogawa, Mark Horowitz:
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. Intelligent Memory Systems 2000: 1-14
Coauthor Index
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