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Conference and Workshop Papers
- 2023
[c6]E. R. Hsieh, Ying-Tsan Tang, Cheng-Rui Liu, Sheng-Min Wang, Y. L. Hsueh, R. Q. Lin, Y. X. Huang, Yu-Ting Chen:
3-bits-per-cell 2T32CFE nvTCAM by Angstrom-laminated Ferroelectric Layers with 10¹¹ Cycles of Endurance and 4.92V of Ultra-wide Memory-windows for In-memory-searching. VLSI Technology and Circuits 2023: 1-2- 2022
- [c5]E. R. Hsieh, J. K. Chang, T. Y. Tang, Y. J. Li, C. W. Liang, M. Y. Lin, S. Y. Huang, C. J. Su, J. C. Guo, Steve S. Chung:
NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFE to Break Great Memory Wall with 10 ns of PGM-pulse, 1010 Cycles of Endurance, and Decade Lifetime at 103 °C. VLSI Technology and Circuits 2022: 359-360 - 2021
- [c4]W. Y. Yang, E. R. Hsieh, C. H. Cheng, B. Y. Chen, K. S. Li, Steve S. Chung:
A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path. IRPS 2021: 1-6 - 2020
- [c3]E. R. Hsieh, H. W. Cheng, Z. H. Huang, C. H. Chuang, S. P. Yang, Steve S. Chung:
A Pulsed RTN Transient Measurement Technique: Demonstration on the Understanding of the Switching in Resistance Memory. IRPS 2020: 1-4 - 2019
- [c2]E. R. Hsieh, C. W. Chang, C. C. Chuang, H. W. Chen, Steve S. Chung:
The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond. VLSI Circuits 2019: 208- - 1977
- [c1]E. R. Hsieh, Robert A. Rasmussen, L. J. Vidunas, W. T. Davis:
Delay test generation. DAC 1977: 486-491
Coauthor Index
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