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ORCIDPeter Lidén
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1990 – 1999
- 1996
[c9]Peter Dahlgren, Peter Lidén:
A fault model for switch-level simulation of gate-to-drain shorts. VTS 1996: 414-421- 1995
- [b1]Peter Lidén:
Fault Simulation and Physical Fault Injection Applied to MOS Transistor Networks. Chalmers University of Technology, Gothenburg, Sweden, 1995 - [c8]Peter Dahlgren, Peter Lidén:
A Switch-level Algorithm for Simulation of Transients in Combinational Logic. FTCS 1995: 207-216 - [c7]Peter Lidén, Peter Dahlgren:
Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers. ISCAS 1995: 2124-2127 - [c6]Peter Lidén, Peter Dahlgren:
Switch-level modeling of transistor-level stuck-at faults. VTS 1995: 208-215 - 1994
- [j1]Johan Karlsson, Peter Lidén, Peter Dahlgren, Rolf Johansson, Ulf Gunneflo:
Using heavy-ion radiation to validate fault-handling mechanisms. IEEE Micro 14(1): 8-23 (1994) - [c5]Peter Dahlgren, Peter Lidén:
Modeling of Intermediate Node States in switch-Level Networks. DAC 1994: 722-727 - [c4]Peter Lidén, Peter Dahlgren, Rolf Johansson, Johan Karlsson:
On Latching Probability of Particle Induced Transients in Combinational Networks. FTCS 1994: 340-349 - 1993
- [c3]Peter Dahlgren, Peter Lidén:
Efficient modeling of switch-level networks containing undetermined logic node states. ICCAD 1993: 746-752 - 1992
- [c2]Peter Lidén, Peter Dahlgren, Jan Torin:
Transistor Fault Coverage for Self-Testing CMOS Checkers. ITC 1992: 476-485 - 1991
- [c1]Johan Karlsson, Ulf Gunneflo, Peter Lidén, Jan Torin:
Two Fault Injection Techniques for Test of Fault Handling Mechanisms. ITC 1991: 140-149
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