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Chung-Hsiang Lin
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2020 – today
- 2022
- [c5]Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang:
PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. ASP-DAC 2022: 122-127
2010 – 2019
- 2015
- [j2]Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang:
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs. ACM Trans. Archit. Code Optim. 12(2): 19:19:1-19:19:24 (2015) - 2012
- [c4]Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang:
SECRET: Selective error correction for refresh energy reduction in DRAMs. ICCD 2012: 67-74 - 2010
- [c3]Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang:
Memory Latency Reduction via Thread Throttling. MICRO 2010: 53-64
2000 – 2009
- 2009
- [j1]Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin:
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. 14(4): 52:1-52:26 (2009) - [c2]Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King:
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. ISLPED 2009: 93-98 - 2006
- [c1]Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King:
Hierarchical value cache encoding for off-chip data bus. ISLPED 2006: 143-146
Coauthor Index
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