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ORCIDJun Yan 0008
Person information
- affiliation: Mathworks Inc., Natick, MA, USA
- affiliation (former): Southern Illinois University Carbondale, Department of Electrical and Computer Engineering, IL, USA
Other persons with the same name
- Jun Yan — disambiguation page
- Jun Yan 0001 — Microsoft Research Asia, Beijing, China (and 1 more)
- Jun Yan 0002
![[0000-0003-4401-7296]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-4401-7296")
— University of Connecticut, Department of Statistics, Storrs, CT, USA (and 1 more) - Jun Yan 0003 — Wuhan University, School of Geodesy and Geomatics, Hubei, China
- Jun Yan 0004 — Chinese Academy of Sciences, CAS-MPG Partner Institute for Computational Biology, Shanghai, China
- Jun Yan 0005 — University of Wollongong, School of Information Technology and Computer Science, NSW, Australia (and 1 more)
- Jun Yan 0006 — Nanjing University of Posts and Telecommunications, College of Telecommunications and Information Engineering, China (and 3 more)
- Jun Yan 0007 — Concordia University, Concordia Institute for Information Systems Engineering, Montreal, QC, Canada (and 1 more)
- Jun Yan 0009 — Chinese Academy of Sciences, Institute of Software, Technology Center of Software Engineering, Beijing, China
- Jun Yan 0010 — Yidu Cloud Technology Co. Ltd., Beijing, China
- Jun Yan 0011 — China University of Geosciences, School of Mechanical Engineering and Electronic Information, Wuhan
- Jun Yan 0012 — University of Southern California, CA, USA (and 1 more)
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2010 – 2019
- 2016
[j12]Jun Yan, Wei Zhang:
Priority L2 cache design for time predictability. Int. J. Embed. Syst. 8(5/6): 427-439 (2016)- 2012
- [j11]Wei Zhang, Jun Yan:
Static Timing Analysis of Shared Caches for Multicore Processors. J. Comput. Sci. Eng. 6(4): 267-278 (2012) - 2011
- [j10]Jun Yan, Wei Zhang:
Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches. J. Comput. Sci. Eng. 5(1): 1-18 (2011) - [j9]Jun Yan, Wei Zhang:
Computing and Reducing Transient Error Propagation in Registers. J. Comput. Sci. Eng. 5(2): 121-130 (2011) - [j8]Jun Yan, Wei Zhang:
An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors. J. Comput. Sci. Eng. 5(2): 131-140 (2011) - 2010
- [j7]Jun Yan, Wei Zhang:
Design and implementation of hybrid multicore simulators. Int. J. Embed. Syst. 4(3/4): 270-275 (2010) - [c6]Jun Yan, Wei Zhang:
Time-Predictable L2 Cache Design for High-Performance Real-Time Systems. RTCSA 2010: 357-366
2000 – 2009
- 2009
- [j6]Yiqiang Ding, Jun Yan, Wei Zhang:
Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. J. Comput. Sci. Eng. 3(1): 59-71 (2009) - [c5]Wei Zhang, Jun Yan:
Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches. RTCSA 2009: 455-463 - 2008
- [j5]Jun Yan, Wei Zhang:
A time-predictable VLIW processor and its compiler support. Real Time Syst. 38(1): 67-84 (2008) - [j4]Jun Yan, Wei Zhang:
Exploiting virtual registers to reduce pressure on real registers. ACM Trans. Archit. Code Optim. 4(4): 3:1-3:18 (2008) - [j3]Jun Yan, Wei Zhang:
Analyzing the worst-case execution time for instruction caches with prefetching. ACM Trans. Embed. Comput. Syst. 8(1): 7:1-7:19 (2008) - [c4]Jun Yan, Wei Zhang:
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches. IEEE Real-Time and Embedded Technology and Applications Symposium 2008: 80-89 - 2007
- [j2]Jun Yan, Wei Zhang:
Hybrid multi-core architecture for boosting single-threaded performance. SIGARCH Comput. Archit. News 35(1): 141-148 (2007) - [j1]Jun Yan, Wei Zhang:
Evaluating instruction cache vulnerability to transient errors. SIGARCH Comput. Archit. News 35(4): 21-28 (2007) - [c3]Jun Yan, Wei Zhang:
Virtual Registers: Reducing Register Pressure Without Enlarging the Register File. HiPEAC 2007: 57-70 - [c2]Jun Yan, Wei Zhang:
WCET analysis of instruction caches with prefetching. LCTES 2007: 175-184 - 2005
- [c1]Jun Yan, Wei Zhang:
Compiler-guided register reliability improvement against soft errors. EMSOFT 2005: 203-209
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