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Journal Articles
- 2011
[j4]Jared Zerbe, Barry Daly, Lei Luo, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara:
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. IEEE J. Solid State Circuits 46(4): 974-985 (2011)- [j3]Jaeha Kim, E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Jared Zerbe, Chih-Kong Ken Yang:
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2096-2107 (2011) - 2009
- [j2]Patrick Satarzadeh, Bernard C. Levy
, Paul J. Hurst:
Digital Calibration of a Nonlinear S/H. IEEE J. Sel. Top. Signal Process. 3(3): 454-471 (2009) - [j1]Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst:
Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 2075-2088 (2009)
Conference and Workshop Papers
- 2019
- [c5]Garen Hovakimyan, Pirooz Hojabri, Gregory A. Martin, Patrick Satarzadeh:
Digital Correction of Time Interleaved DAC Mismatches. ISCAS 2019: 1-5 - 2012
- [c4]Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi:
A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS. ISSCC 2012: 158-160 - 2010
- [c3]Jaeha Kim, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Ali-Azam Abbasfar, Jared Zerbe:
Equalizer design and performance trade-offs in ADC-based serial links. CICC 2010: 1-8 - [c2]Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst:
A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs. ISCAS 2010: 4053-4056 - 2007
- [c1]Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst:
Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter. ISCAS 2007: 1705-1708
Coauthor Index
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