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Béla Fehér
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Journal Articles
- 2008
- [j4]Péter Szántó, Gábor Szedö, Béla Fehér:
High-Performance Timing-Driven Rank Filter. VLSI Design 2008: 753043:1-753043:6 (2008) - 2005
- [j3]Mark F. St. John, Harvey S. Smallman, Daniel I. Manes, Béla Fehér, Jeffrey G. Morrison:
Heuristic Automation for Decluttering Tactical Displays. Hum. Factors 47(3): 509-525 (2005) - 2003
- [j2]Lörinc Antoni, Régis Leveugle, Béla Fehér:
Using run-time reconfiguration for fault injection applications. IEEE Trans. Instrum. Meas. 52(5): 1468-1473 (2003) - 1993
- [j1]Béla Fehér:
Efficient synthesis of distributed vector multipliers. Microprocess. Microprogramming 38(1-5): 345-350 (1993)
Conference and Workshop Papers
- 2011
- [c12]Imre Pechan, Béla Fehér:
Molecular Docking on FPGA and GPU Platforms. FPL 2011: 474-477 - 2009
- [c11]Béla Fehér, Tamás Raikovich, György Dancsi, Péter Laczkó:
LOGSYS: A simple tool for complex student projects. MSE 2009: 33-36 - 2006
- [c10]Péter Szántó, Béla Fehér, Gábor Szedö:
High Performance Timing-Driven Rank Filter. ICECS 2006: 752-755 - [c9]Ákos Lédeczi, Gergely Kis, Béla Fehér, Péter Völgyesi, György Balogh:
Acoustic Source Localization Fusing Sparse Direction of Arrival Estimates. WISES 2006: 141-153 - 2004
- [c8]Péter Szántó, Béla Fehér:
High performance visibility testing with screen segmentation. ESTIMedia 2004: 75-80 - 2003
- [c7]Régis Leveugle, Lörinc Antoni, Béla Fehér:
Dependability Analysis: A New Application for Run-Time Reconfiguration. IPDPS 2003: 173 - [c6]Péter Szántó, Béla Fehér:
3D rendering using FPGAs. VLSI-SOC 2003: 149-154 - 2002
- [c5]Lörinc Antoni, Régis Leveugle, Béla Fehér:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. DFT 2002: 245-253 - 2000
- [c4]Lörinc Antoni, Régis Leveugle, Béla Fehér:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. DFT 2000: 405-413 - [c3]Tamás Szabó, Lörinc Antoni, Gábor Horváth, Béla Fehér:
A Full-Parallel Digital Implementation for Pre-Trained NNs. IJCNN (2) 2000: 49-54 - 1998
- [c2]Béla Fehér, Gábor Szedö:
Cost Effective 2×2 Inner Product Processors. FPL 1998: 348-355 - [c1]Tamás Szabó, Béla Fehér, Gábor Horváth:
Neural network implementation using distributed arithmetic. KES (3) 1998: 510-518
Coauthor Index
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