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Journal Articles
- 2007
[j6]Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe:
Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles. IEICE Trans. Inf. Syst. 90-D(2): 395-402 (2007)- 2006
- [j5]Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe:
An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3416-3426 (2006) - 2003
- [j4]Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura, Katsumasa Watanabe:
Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3184-3191 (2003) - 2002
- [j3]Shinji Kimura, Atsushi Ishii, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara, Katsumasa Watanabe:
Look Up Table Compaction Based on Folding of Logic Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2701-2707 (2002) - 1988
- [j2]Tatsuo Tsuji, Katsumasa Watanabe, Athushi Ikehata:
Structured FORTRAN Preprocessors Generating Optimized Output. Softw. Pract. Exp. 18(5): 427-442 (1988) - 1987
- [j1]Tatsuo Tsuji, Kazuto Kontani, Katsumasa Watanabe, Mitsuaki Sumiya:
A method of constructing large-scale program processor for 8-bit system utilizing memory mapping feature. Syst. Comput. Jpn. 18(10): 35-46 (1987)
Conference and Workshop Papers
- 2006
- [c10]Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe:
A New Approach to Online FPGA Placement. CISS 2006: 145-150 - [c9]Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe:
Robust Quantum Algorithms with epsilon-Biased Oracles. COCOON 2006: 116-125 - 2005
- [c8]Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita:
Event-oriented computing with reconfigurable platform. ASP-DAC 2005: 1248-1251 - [c7]Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe:
Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. ERSA 2005: 225-234 - 2001
- [c6]Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe:
A real-time 64-monosyllable recognition LSI with learning mechanism. ASP-DAC 2001: 31-32 - [c5]Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe:
Speech recognition chip for monosyllables. ASP-DAC 2001: 396-399 - 2000
- [c4]Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe:
An application specific Java processor with reconfigurabilities. ASP-DAC 2000: 25-26 - [c3]Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe:
Multi-clock path analysis using propositional satisfiability. ASP-DAC 2000: 81-86 - 1998
- [c2]Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe:
Waiting false path analysis of sequential logic circuits for performance optimization. ICCAD 1998: 392-395 - 1997
- [c1]Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya:
A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. CODES 1997: 147-151
Coauthor Index
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