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Chandra Mulpuri
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2010 – 2019
- 2017
- [c4]Stephen Yang, Chandra Mulpuri, Sainath Reddy, Meghraj Kalase, Srinivasan Dasasathyan, Mehrdad E. Dehkordi, Marvin Tom, Rajat Aggarwal:
Clock-Aware FPGA Placement Contest. ISPD 2017: 159-164 - 2016
- [c3]Stephen Yang, Aman Gayasen, Chandra Mulpuri, Sainath Reddy, Rajat Aggarwal:
Routability-Driven FPGA Placement Contest. ISPD 2016: 139-143
2000 – 2009
- 2002
- [c2]Srihari Cadambi, Chandra Mulpuri, Pranav Ashar:
A fast, inexpensive and scalable hardware acceleration technique for functional simulation. DAC 2002: 570-575 - 2001
- [c1]Chandra Mulpuri, Scott Hauck:
Runtime and quality tradeoffs in FPGA placement and routing. FPGA 2001: 29-36
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last updated on 2024-04-24 22:57 CEST by the dblp team
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