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ORCIDMasaru Kato
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2010 – 2019
- 2012
[c8]Masao Inui, Masaru Kato, Keitaro Inomata, Machiko Sato, Yoshihiko Azuma, Daisuke Saito, Tota Mizuno, Takao Kikuchi, Sakuji Yoshimura:
Correcting for non-uniform illumination when photographing the mural in the royal tomb of Amenophis III (III) Correcting mural images. CGIV 2012: 92-96- 2010
- [c7]Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano:
MuCCRA-3: a low power dynamically reconfigurable processor array. ASP-DAC 2010: 377-378 - [c6]Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano:
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. FPT 2010: 349-352
2000 – 2009
- 2009
- [c5]Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano:
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. ERSA 2009: 283-286 - [c4]Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano:
Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. FPL 2009: 530-533 - [c3]Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano:
Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. FPT 2009: 104-111 - 2008
- [c2]Masaru Kato, Yohei Hasegawa, Hideharu Amano:
Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs. ERSA 2008: 215-221 - [c1]Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano:
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. FPL 2008: 215-220
Coauthor Index
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