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2010 – 2019
- 2016
[c10]Juexiao Su, Ju-Yueh Lee, Chang Wu, Lei He:
In-place LUT polarity inVersion to mitigate soft errors for FPGAs. DFT 2016: 81-86- 2012
- [j2]Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He:
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. 18(1): 13:1-13:18 (2012) - [c9]Ju-Yueh Lee, Cheng-Ru Chang, Naifeng Jing, Juexiao Su, Shi-Jie Wen, Rick Wong, Lei He:
Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs. FPT 2012: 23-28 - 2011
- [j1]Wenyao Xu, Jia Wang, Yu Hu, Ju-Yueh Lee, Fang Gong, Lei He, Majid Sarrafzadeh:
In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1372-1381 (2011) - [c8]Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He:
Fault modeling and characteristics of SRAM-based FPGAs (abstract only). FPGA 2011: 279 - [c7]Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He:
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL 2011: 282-285 - [c6]Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He:
Mitigating FPGA interconnect soft errors by in-place LUT inversion. ICCAD 2011: 582-586 - 2010
- [c5]Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li
:
Fault-tolerant resynthesis with dual-output LUTs. ASP-DAC 2010: 325-330 - [c4]Samuel B. Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He:
RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications. DATE 2010: 783-788 - [c3]Ju-Yueh Lee, Zhe Feng, Lei He:
In-place decomposition for robustness in FPGA. ICCAD 2010: 143-148
2000 – 2009
- 2009
- [c2]Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He:
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. ISQED 2009: 702-707 - 2006
- [c1]Kun-Lin Tsai, Ju-Yueh Lee, Shanq-Jang Ruan, Feipei Lai:
Low power scheduling method using multiple supply voltages. ISCAS 2006
Coauthor Index
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