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Journal Articles
- 2018
[j4]Faisal Mustafa Sajjade
, Neeraj Kumar Goyal, B. K. S. V. L. Varaprasad, Ravindra Moogina:
Radiation Hardened by Design Latches - A Review and SEU Fault Simulations. Microelectron. Reliab. 83: 127-135 (2018)- 2007
- [j3]B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal:
A New ATPG Technique (ExpoTan) for Testing Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 189-196 (2007) - 2004
- [j2]B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal:
A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 273-287 (2004) - 2001
- [j1]B. K. S. V. L. Varaprasad, L. M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal:
An Efficient Test Pattern Generation Scheme for an On Chip BIST. VLSI Design 12(4): 551-562 (2001)
Conference and Workshop Papers
- 2023
- [c2]Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh:
TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. IOLTS 2023: 1-7 - 2022
- [c1]Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh:
REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. ISVLSI 2022: 394-397
Coauthor Index
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